1. Field of the Invention
The present invention relates to a cascode circuit used in a high frequency circuit, and an integrated circuit having the cascode circuit.
2. Description of the Related Art
Cascode circuit, which includes field-effect transistors (hereinafter, referred to as “FETs”) cascode-connected successively (hereinafter, referred to as “cascode FET”), is used in a high frequency amplifier circuit of such as a cellular phone. The cascode circuit includes a first FET, a second FET and a capacitor. A source terminal of the first FET is grounded, a drain terminal of the first FET is connected to a source terminal of the second FET. A gate terminal of the first FET, the source terminal of the first FET, and a drain terminal of the second FET function as a gate terminal, a source terminal, and a drain terminal of the cascode circuit, respectively. A gate terminal of the second FET is grounded through a capacitor. As to this, refer to “Cascode Connected AlGaN/GaN HEMT's on SiC Substrates” by Bruce M. Green, IEEE Microwave and Guided Wave Letters, vol 10, No. 8, p 316 to 318, August 2000 (hereinafter, referred to as “document 1”), and Japanese Laid-open Patent Publication No. 6-224647 (hereinafter, referred to as “document 2”), for example. The gate terminal of the first FET is connected to a gate voltage setting terminal. By using the gate voltage setting terminal, a direct current voltage is applied to the gate terminal of the first FET. A voltage of 0 V is normally applied to the gate voltage setting terminal, but a desired voltage may be applied thereto in some cases.
A drain terminal of the second FET is connected to a high voltage power supply. If the second FET is used alone, it is necessary to DC-DC convert the power supply voltage to reduce it, and supply the reduced voltage to the drain terminal of the second FET, because a withstand voltage of the single FET is generally as low as 10 to 30 V. However, if the cascode FET in which two FETs are connected successively is used, it becomes unnecessary to reduce the power supply voltage, because the withstand voltage between the drain and source terminals of the cascode FET becomes two times between the drain and source terminals of a single FET. As a result, in the case where the cascode FET is used, it is possible to reduce conversion loss caused by above-mentioned DC-DC conversion, so that the efficiency of the whole system including the cascode FET can be enhanced.
However, in the cascode circuit as disclosed in documents 1 and 2, a capacitance value of the capacitor is set large, so that the gate terminal of the second FET is short-circuited with respect to high frequency. Therefore, there is a problem that a voltage between the drain and source terminals of the first FET is maintained constant, so that the cascode circuit can not output a voltage proportional to the operation voltage thereof. Further, in such a cascode circuit, there is also a problem that only the voltage between the drain and source terminals of the second FET is varied within a narrow width (voltage amplitude), so that the output voltage of the cascode circuit is low. As a result, even if the operation voltage of the cascode circuit is increased, the amplitude of the voltage between the drain and source terminals of the cascode circuit is low, so that the output power of the cascode circuit is low and the efficiency thereof is low.
On the other hand, the Japanese Patent No.3169775 discloses an integrated circuit having a FET for use in a high frequency circuit.